The present invention relates to a semiconductor memory device and more particularly, a semiconductor memory device comprising memory cell units, such as a NAND cell, an AND cell, a DINOR cell and the like, wherein a plurality of memory cells are connected to one another.
As a kind of semiconductor memory cells, EEPROMs which are electrically rewritable are known. Among them, an NAND cell type EEPROM, in which plural memory cells are connected to each other in series to construct a NAND cell block, has drawn attention since it can be highly integrated.
One memory cell of a NAND cell type EEPROM (hereinafter referred to as NAND cell) has a FETMOS structure in which a floating gate (charge storage layer) and a control gate are stacked in a layered manner on a semiconductor substrate with an insulating film interposing therebetween. Plural memory cells in the structure are serially connected to each other in such a manner that a source or a drain is shared between memory cells adjacent to each other, whereby a NAND cell is constructed. Such NAND cells are configured in a matrix to form a memory cell array.
Drains at one side of NAND cells are connected to a bitline through a select gate transistor in such a manner that drains on the one side of the NAND cell adjacent to a bitline are commonly connected to the bitline, whereas sources on the other side are connected to a common source line each through a select gate transistor. Control gates of memory cell transistors (hereinafter referred to as cell transistor) disposed along a row direction of a memory cell array are commonly connected to one another to constitute a word line. On the other hand gate electrodes of select gate transistors disposed along a row direction are commonly connected to one another to constitute a select gate line.
Well known examples of a non-volatile semiconductor memory device using such a conventional NAND cell are disclosed in K. D. Suh et al., "A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme", IEEE. J. Solid-State Circuits, vol. 30, pp. 1149 to 1156, Nov. 1995 (Reference 1) and Y. Iwata et al., "A 35 ns Cycle Time 3.3 V Only 32 Mb NAND Flash EEPROM", IEEE J. Solid-State Circuits, vol. 30, pp. 1157 to 1164, Nov. 1995 (Reference 2) and the like.
Operations in a non-volatile semiconductor memory device using a conventional NAND cell are described in the reference 1. The content will be described in reference to FIGS. 1 to 3B.
FIG. 1 is a block diagram showing a construction of a memory cell array and FIG. 2 is a detailed block diagram of a page buffer P/B in FIG. 1. FIG. 3A and FIG. 3B are a diagram and a table showing operations of erase, read and programming in biased conditions. In FIGS. 1 to 3B, BSEL indicates a block select signal, BL0 to BL4223 indicate bitlines, CSL indicates a source line, CGO to CG15 indicate common gate lines, SSL and GSL respectively indicate select gate lines on the bitline and source line sides and WL0 to WL15 respectively indicate word lines. In FIG. 3A and FIG. 3B, PassWL and SelWL respectively indicate a non-selected (pass) word line and a selected word line. The block select signal BSEL is output from a block decoder, which selects a memory cell block. In the page buffer P/B, a latch circuit as a sense amplifier connected to each bitline is provided, as shown in FIG. 2.
In an erase operation, the common gate lines CG0 to CG15 in FIG. 1 are grounded. A block select signal BSEL is at a high level (a power supply voltage) a block select signal of a non-selected block is maintained at a low level (the ground potential). Therefore, a word line in the non-selected block is at the ground potential and a word line in the non-selected block is in a floating state.
Then, an erase pulse of 21 V and 3 ms is applied to a bulk (a p-well in which a memory cell is formed). As a result, in the selected block, an erase voltage (21 V) is applied between the p-well and a word line, electrons in a floating gate flow into the p-well by an FN (Fowler-Nordheim) tunnel current and a threshold voltage of the memory cell becomes almost -3 V. Since an excessive erase is not problematic in a NAND type flash, a memory cell is erased deeply to the order of -3 V with one erase pulse.
On the other hand, a non-selected block is not affected by an erase pulse because of a presence of capacitive coupling between a word line in a floating state and a p-well. The source of a transistor for which a block select signal BASEL is supplied, a metal interconnect between the source and a word line made of polysilicon and the control gate made of polysilicon are connected to the word line in a floating state. A coupling ratio is calculated from a capacitance connecting the word line in a floating state. As the capacitance, there are related to: a source junction capacitance of a transistor for whose gate a block select signal is supplied; an overlap capacitance between the source and the gate; a capacitance between polysilicon and metal interconnection on the field; a capacitance between a control gate made of silicon and a p-well; and the like. Among them, the capacitance between a control gate made of silicon and the p-well is conspicuously large so as to occupy a greater part of the total magnitude. For this reason, a coupling ratio obtained from actually measured results was as large as about 0.9 and a FN tunnel current can be prevented from flowing. Erase verify to confirm an end of erase can be decided by whether or not a threshold voltage of each of all the memory cells in a selected block is reduced to be equal to or less than -1 V.
In a read operation, cell data of one page are simultaneously transferred to a latch circuit in a page buffer and successively read out. FIG. 4 is a waveform diagram showing operational signals in a read operation. The cell data of one page are sensed, the page buffer is at "0" in the first stage, that is at a low level and initialized to a condition where the data in the memory cell are read. At this point, a bit line is at 0 V, a select gate lines SSL, GSL are at 4.5 V (time of t1 of FIG. 4). Thereafter, a selected word line in the selected block (NAND cell) and a non-selected word line in the selected block are respectively supplied with pass voltages of 0 V and 4.5 V (time of t2 of FIG. 4). The voltage 4.5 V supplied for the non-selected word line is higher than a threshold voltage of each cell after programming and erase and thereby all the non-selected cells each works as a pass-transistor.
On the other hand, only a cell transistor which has been erased is conductive because of a selected word line applied with 0 V. Therefore, a NAND cell in which a cell after erase is read out works as a pass to bias a bitline to the ground potential and a NAND cell in which a cell after programming is read out works so as to place the bit line in an open condition. At a time t3 shown in FIG. 4, a direct sense route from the bitline to a latch circuit is intercepted by making a signal PGM shown in FIG. 2 low in level. For this reason, latch data is determined only through a transistor for sense. A load in a PMOS current-miller circuit CM which supplies a load current at 2 .mu.A to a bitline at a reference voltage Vref is activated. A bitline which reads a cell after erase keeps a low level, since a load current flows, and a bitline which reads a cell after programming becomes a high level. The bitline which reads a cell after programming makes the transistor Tr for sense conductive and therefore, the latch circuit is reversed to "1" (t4).
In such a manner, a latch circuit having read data from a written cell stores data "1" and a latch circuit having read data from an erased cell stores data "0." These latch data pass through a read circuit and then transformed into a normal logic level. Therefore, after all the latch circuits of one page are simultaneously set, continuous read can be made possible.
In a programming operation, programming data are continuously loaded on a page buffer. The data "0" is cell data for programming and the data "1" is cell data to prohibit programming. The cycle of programming is repeated till all the latched data "0" are programmed in all the cells. Each programming cycle comprises a programming operation and a verify operation in which excessive programming is prevented in a cell in which "0" is programmed. In a more detailed manner, a programming cycle of 40 .mu.s comprises the following steps of:
(1) Bitline set up (8 .mu.s): A level of a bitline is set at 0 V according to programming data in a page buffer (latch circuit) and when programming is prohibited, the level is set at Vcc. PA1 (2) Programming (20 .mu.s): A programming voltage is input as a short pulse in a selected word line. PA1 (3) Discharge of a word line (4 .mu.s): A high voltage of a selected word line is discharged and the selected word line is prepared for input for of a successive low verify potential. PA1 (4) Programming verify (8 .mu.s): Whether or not a threshold voltage of a programming cell is programmed to an extent equal to or more than a target value. PA1 (1) The precharge voltage is generated by a booster circuit provided in the semiconductor memory device. PA1 (2) The precharge voltage is supplied from an outside of the semiconductor memory device. PA1 (3) The precharge circuit comprises: an n-channel MOS transistor in which the source is connected to the bitline and the drain is connected to the precharge voltage supply mode. PA1 (4) The voltage generating circuit supplies a voltage higher than the precharge voltage to the gate of the MOS transistor constituting the precharge circuit, all the word lines of the selected memory cell unit and the select gate line in a programming. PA1 (5) The control circuit electrically disconnects the precharge circuit from the bitline in the second operation. PA1 (6) The control circuit reduces potential of a word line in which the programming voltage is supplied to the adjacent word line to a voltage equal to or lower than the power supply voltage in the second operation. PA1 (7) The control circuit reduces potentials of a word line in which the programming voltage is supplied to the adjacent word line and the select gate line connected to the select gate to a voltage equal to or lower than the power supply voltage in the second operation. PA1 (8) The control circuit electrically disconnects the precharge circuit from the bitline in the third operation. PA1 (9) A load transistor connected between the second node of the bitline and a electric source for suppressing reduction in potential of the bitline is further provided, and the control circuit executes an operation in which the load transistor is made conductive and reduction in potential of the bitline through which programming is prohibited is suppressed in control of potentials of the bitline and the channel of the memory cell based on programming data held in the latch circuit in the third operation. PA1 (10) The control circuit executes the third operation after executing the second operation. PA1 (11) The control circuit executes the second operation after executing the third operation. PA1 (1) The potential supplied to the non-programming bitline is a power supply voltage in a chip or that supplied from an outside of the chip. PA1 (2) The voltage generating circuit generates the first voltage higher than a power supply voltage by the threshold voltage of the select gate or the memory cell, and the first voltage is supplied to the select gate line or the word line from the voltage generating circuit in programming of data to the memory cell. PA1 (3) In programming of data to the memory cell, after the channels of the memory cells are charged to the precharge voltage higher than the differential voltage between potential of the non-programming bitline and the threshold voltage of the select gate, a voltage supplied to the select gate line is reduced to make the select gate is cut off. PA1 (4) In programming of data to the memory cell, after the channels of the memory cells are charged to the precharge voltage higher than the differential voltage between potential of the non-programming bitline and the threshold voltage of the select gate, a voltage supplied to the select gate line is reduced to a second voltage equal to or lower than the power supply voltage and equal to or higher than a threshold voltage of the select gate from the first voltage and the select gate is cut off. PA1 (5) A timing at which the voltage supplied to the select gate line is reduced to the second voltage from the first voltage; a timing at which the programming voltage is supplied to a selected word line; and a timing at which potential of a non-selected word line of a selected memory cell unit is increased to about half the programming voltage are almost the same.
In a verify operation, a latch circuit in which programming has sufficiently been effected, changes the data "0" to the data "1" and prevents from being programmed. A bias condition in a verify operation is almost the same as that in a read operation, but data in a programming condition is held in the latch circuit and a voltage 0.7 V other than 0 V is supplied for a selected word line. In this condition, when a threshold voltage of a programming cell is in excess of 0.7 V, that is when programming is sufficiently effected, data in the latch circuit is changed from the data "0" to the data "1." Since the latch circuit which has latched the data "1" only performs a change from the data "0" to the data "1" in a verify operation, no influence receives in the verify operation. A cycle of programming is repeated till all the latch circuits in the page buffer come to hold the data "1" or till it reaches the maximum programming time period of 10 cycles.
FIG. 5 shows bias conditions for a programming prohibiting potential which is supplied to the channel of a selected cell. A transistor of a select gate line SSL on the bitline side is a conductive condition, a transistor of a select gate line GSL on the source line side is in a non-conductive condition, a bitline of a cell to be programmed is set at 0 V, and a bitline of a cell prohibited from programming is set at V.sub.cc. Each channel of the NAND cell is biased to the ground potential by the bitline supplied with a voltage 0 V. When a programming voltage is applied to the gate of a select cell, a large potential difference arises between the floating gate and the channel, so that electrons are injected by a FN tunnel current into the floating gate. In the cell prohibited from programming, since a power supply voltage V.sub.cc is applied to a bitline, a channel of a select NAND cell is precharged. When a word line of the selected NAND cell, that is, a selected word line to be input with a programming voltage, and a non-selected word line to be input with a pass voltage are activated, a capacitance of the channel is automatically increased in voltage by series coupling of capacitances among a word line, a floating gate, a channel and p-well. In such a manner, a channel voltage of a NAND cell prohibited from programming in a selected block is determined by capacitive coupling between the word line and the channel.
Therefore, in order to sufficiently increase a programming prohibiting potential, it is important to effect sufficient initial charge of the channel or to increase a coupling ratio between the word line and the channel.
A coupling ratio B between a word line and a channel is calculated in the following way: EQU B=Cox/(Cox+Cj),
wherein Cox is a total of gate capacitances between the word line and the channel and Cj is a total of junction capacitances of a source and a drain in a cell transistor. A channel capacitance of a NAND cell is a sum of the total of gate capacitances and the total of the junction capacitances. An overlap capacitance between a select gate and a source, a capacitance between a bitline and a source or a drain and the like are very small, compared with the whole of the channel capacitances and therefore neglected here.
In the case of a 64 Mb NAND cell with a 0.4 .mu.m rule, W (a gate width)/L (a gate length)=0.4 .mu.m/0.38 .mu.m in a transistor and a pitch of word line is 0.76 .mu.m. In this NAND cell type EEPROM, a gate capacitance C.sub.ox and junction capacitance Cj are almost equal to each other and a coupling ratio is 0.5. The junction capacitance changes more or less according to processing conditions, such as impurity concentrations of a p-well, a source and drain of a cell transistor and the like. On page 1153 of the reference 1, there is disclosed that a coupling ratio is 80%, and in order to realize this ratio, for example, a junction capacitance Cj is required to be one-fourth of a conventional value. However, in order to decrease the junction capacitance, it is required to make an impurity concentration of a p-well smaller or to make impurity concentrations of source and drain smaller. The former has a limitation, since it requires a decrease in field withstand voltage between memory cells. The latter decesses a cell current because it makes a resistance between the source and drain increased.
A method in which a gate capacitance Cox is increased but a junction capacitance is decreased is described in Shirota et al., "A 2.3 .mu.m.sup.2 Memory Cell Structure for 16 Mb NAND EEPROMs", in IEDM '90 technical Digest, pp. 103 to 106, Dec. 1990 (Reference 3). In the reference 3, a method in which a width of a word line (a channel length of a cell transistor) is broadened and a space between adjacent word lines is smaller with no change in a pitch of word line. This method has a problem in fabrication.
There is another method in which a p-well in which a cell is formed is biased negative in programming and thereby a depletion layer for a junction capacitance is extended, so that the junction capacitance is decreased. However, since the junction capacitance is approximately proportional to a reciprocal of a square root of a sum between a built-in voltage and a reverse bias of the junction, even if 2 V is applied to a p-well with a channel voltage of 6 V, the junction capacitance is only decreased to about 90% of the case where this method is not applied and a large effect cannot be expected. Moreover, to actually perform this method, there are more circuits and more power to give a negative bias to the p-well.
As mentioned above, while there are various methods to increase a coupling ratio, each method has a problem.
Besides, in the reference 2 and T. Tanaka et al., "A Quick Intelligent Program Architecture for 3 V Only NAND-EEPROM's", in Symp. VLSI Circuits Dig. Tech. Papers, June 1992, pp. 20 to 21 (Reference 4), a method in which a channel voltage of a NAND cell prohibited from programming in a programming operation is supplied in a way different from the reference 1. In the reference 1, a channel voltage is increased by a capacitive coupling between a channel in a floating state and a word line. On the other hand, in the references 2 and 4, a programming prohibiting potential which is boosted by a charge pump in a peripheral circuit of a chip is directly supplied to the channel through a bitline.
FIG. 6 is a circuit showing a sense amplifier comprising a memory cell and a bitline, and FIG. 7 shows bias conditions for erase, read and programming operations of a NAND cell. In a programming operation of selected NAND cell, by a sense amplifier, Vpp (18 V) is applied to a selected word line CG6 (control gate line), Vm (10 V) is applied to non-selected word lines CG1 to CG5 and CG7 to CG8 and a select gate SG1, 0 V is applied to a bitline in which programming is performed and Vmb (8 V) is applied to a bitline in which programming is not performed. Therefore, a channel of a NAND cell prohibited from programming is supplied through a bitline and a select gate line with a fixed voltage of 8 V. At this point, while the voltage Vm of a select gate line and a non-selected word line is 2 V higher than that of a bit line in which programming is not performed, the reason why is that a threshold voltage of the select gate, which is 2 V, and a threshold voltage of a programmed cell, when it is located closer to the bitline side of a NAND cell than a cell to be programmed, are considered.
There are named the following two problems in the references 2 and 4. A first problem is that a programming prohibiting potential is supplied to a bitline from a sense amplifier. For this reason, a transistor constituting the sense amplifier is required to be a high voltage transistor. In the case where a power supply voltage V.sub.cc is 3.3 V, a transistor into which the power supply voltage V.sub.cc is input has a gate oxide film, for example, as thin as 120 .ANG.. Therefore, a gate length is short, that is a design rule, for example as severe as 0.4 .mu.m can be adopted for a design.
On the other hand, a transistor which can endure a programming prohibiting potential of 8 V has, for example, an oxide film thickness as thick as 200 .ANG. and a gate length as long as 1 .mu.m. That is, this transistor is required to design using a rule as mild as, for example 1 .mu.m. Thus an area for layout for a sense amplifier is increased and it becomes hard to layout a sense amplifier in a corresponding manner to a fine bitline.
A second problem is that a high voltage, in which threshold voltages of a non-selected word line and a select gate line are considered, is required to be applied to the non-selected word line and the select gate line, which works a pass transistor, in order to input a programming prohibiting potential through a bitline to a channel. To increase a voltage of the non-selected word line brings about a problem that errors arise in programming a non-selected cell of a NAND cell to be programmed. Therefore, a problem further arises that a programming prohibiting potential is limited to a voltage at which no errors arise in programming, so that an allowable range (window) of a programming prohibiting potential is narrower. Moreover, when a select gate line is increased, the gate oxide film receives a larger electric field, since the channel of the NAND cell which performs programming has a voltage Vcc, which causes a break down of an oxide film of the select gate.